The invention relates to driver integrated circuits for driving active matrix circuits accommodated in liquid crystal display devices, and more particularly to such circuits using a multi-level driver system.
Active matrix type liquid crystal displays are well known in the art. Such display device essentially comprises active matrix circuits, driver integrated circuits and power supply circuits. In the prior art, a sample-and-hold circuit system which includes sample-and-hold circuits and buffers has been used as a driving system for such display device. The sample-and-hold circuit system uses only analog signals as data which is unsuitable for a high speed performance of the display device as compared with digital signals. The analog signals exhibit a fluctuation of a voltage which affects device performances. Further, the sample-and-hold circuit system requires a reset operation.
To combat those disadvantages, a multi-level driver system which uses only digital signals as data was proposed. The multi-level driver system has a plurality of power supplies, each of which supplies a predetermined voltage to the active matrix circuits thereby permitting any one of plural different voltage levels to be selected.
The prior art of such multi-level driver system will now be described with reference to FIG. 1. Equivalent circuits to the active matrix circuits accommodated in the liquid crystal display device essentially comprises gate lines 301 serving as scanning lines, drain lines 303 serving as voltage signal transmission lines, thin film transistors 307 serving as switching devices and pixel capacitors 306 having opposite electrodes 308 which store the voltage signals. Both the pixel capacitors 306 and the thin film transistors 307 are aligned in a matrix. To drive the active matrix circuits, the liquid crystal display device accommodates a plurality of drain line driver integrated circuits 304 connected to the drain lines 303 and a plurality of gate line driver integrated circuits 302 connected to the gate lines 301. Further, a power supply circuit 305 generates a plurality of predetermined voltage levels. The drain line driver integrated circuits 304 are connected in series to the power supply circuit 305.
Each of the drain line driver integrated circuits 304 selects any one of various voltage levels supplied from the power supply circuit 305 and transmits the selected level voltage as voltage signals to the drain lines 303. Concurrently, each of the gate line driver integrated circuits 302 applies voltage pulses to the gate lines 301 to accomplish the scanning of the display. As a result of the scanning, thin film transistors 307 which are applied with the voltage pulse are taken into ON state. Then, the voltage signals applied to the drain line 303 are transmitted through the thin film transistor 307 to the pixel capacitor 306, after which thin film transistor 307 turns OFF to store the voltage signal in the pixel capacitor 306. This results in an accomplishment of write operations to the active matrix circuits. Generally, the gray level of each of plural pixels involved in the display devise is associated with the voltage level stored in the pixel capacitor.
Circuit performances of the drain line driver integrated circuits 304 are described with reference to FIG. 2. Any one of the above plural drain line driver circuits 304 is selected by a chip selector circuit 401 which is controlled by grouped control signals 402. A shift register 403 is applied with a clock signal 404. The shift register 403 is controlled by the chip selector circuit 401 and the grouped control signals 402 to generate scanning pulses by which a data transmission shift register 405 is scanned. The data transmission shift register 405 stores digital signals of the gray levels of the pixels. Normally, digital signals of colors are based so that digital signals of red, green and blue colors are allocated in a column. This requires a signal input timing to be controlled by the shift register 403. If a monochrome display is accomplished, the shift register 403 may be omitted. A latch circuit 407 fetches and reads concurrently the digital signals allocated on a line from the data transmission shift register 405 in which a latch timing is controlled by signals transmitted through a signal line 408. The latch circuit 407 outputs the above digital signals which have been fetched and concurrently fetches digital signals allocated on a next line from the data transmission shift register 405. A multi-level driver 409 is connected to plural power supplies 305 through power transmission lines 410. The multi-level driver 409 receives digital signals from the latch circuit 407, after which the multi-level driver 409 selects any one of plural power transmission lines 410 connected to the power supplies 305. The voltage signals supplied from the selected power supply are transmitted through output terminals 411 to the drain lines 303.
The operations of the multi-level driver 409 in case of eight gray levels will subsequently be described with reference to FIG. 3. In this case, digital signals comprising three bits are required for each pixel to accomplish the eight gray level display. A latch circuit 501 stores digital data D1, D2 and D3. An address decoder 502 fetches the digital data D1, D2 and D3 followed by decoding the digital data. Subsequently, the address decoder 502 outputs selective signals to selective signal lines 505. The selective signals serve to operate a plurality of analog switches 504, and thus any one of the analog switches 504 turns ON thereby selecting any one of voltage levels V0 to V7 supplied from the plural power supplies 503. Thus, the selected voltage level is transmitted as a voltage signal through the selected analog switch 504 to a voltage signal transmission line. The voltage signal is further transmitted to the active matrix circuits through an analog switch 506 which is controlled by gate pulse applied to a gate terminal 507.
When any one of the voltage levels is selected and outputted as the voltage signal, the analog switch 506 turns ON by gate pulses applied to the gate terminal 507 so that the voltage signal supplied from the external voltage supply 503 is transmitted to a thin film transistor 508 through the drain line 303 involved in the active matrix circuits. The thin film transistor 508 serves as a switching device in the active matrix circuits and controlled by a gate pulse applied to a gate terminal 509. The gate line driver integrated circuits 302 apply voltage pulses to the gate lines 301 whereby the thin film transistors 508 are taken into ON state. Subsequently, the voltage signal is transmitted through the thin film transistor 508 serving as the analog switch to a pixel capacitor 510. The pixel capacitor 510 including an opposite electrode 511 stores the voltage signal of any of voltage levels V0 to V7. Since the gray levels of the pixel are associated with the voltage levels V0 to V7 stored in the pixel capacitor 510, the number of gray levels corresponds to the number of the voltage levels, and thus to the number of power supplies. In this case, since eight voltage levels V0 to V7 exist, the display of eight gray levels is thus accomplished.
In the prior art, the accomplishment of a high gray level display requires a large number of power supplies which correspond to the number of gray levels. The number of power supplies defines the number of gray levels in this multi-level driver system. By the way, the sample-and-hold circuit system permits infinite gray levels in view of idealization. Generally, the driver integrated circuits of the multi-level driver system accommodate a large number of signal lines, typically 120 to 200 output lines. Such display devices are likely to limit the gray levels to eight gray levels. In the prior art, the accomplishment of a high gray level display renders such display device unreasonable. For instance, the accomplishment of the sixteen gray level display renders the circuit scale twice approximately, much less the thirty two or sixty four gray level displays are of no utility in view of circumstances. Further, the gray levels of the multi-level driver system correspond to the voltage levels stored in the pixel capacitor. The accomplishment of a large number of gray levels requires a large number of voltage levels. Thus, such high gray level display device is also required to accommodate a large number of power circuits thereby causing a higher cost and a high power consumption.